Efficient Architecture for SPIHT Algorithm in Image Compression

A arithmetic coder architecture with a high throughput memory efficient for set partitioning in hierarchical trees is proposed in this paper. This paper also presents a throughput efficient image compression using ‘Set Partitioning in Hierarchical Trees’ (SPIHT) algorithm for compression of images. The SPIHT use inherent redundancy among wavelet coefficients and suited for both gray and color image. The SPIHT algorithm uses dynamic data structures which hinders hardware realizations. In this FPGA implementation have modified basic SPIHT in two ways, one by using static (fixed) mappings which represent significant information and the other by interchanging the sorting and refinement passes. A hardware realizations is done in a Xilinx XC3S200 device. As one part of the hardware realization, the SPIHT algorithm was implemented in software side. In this matlab GUI (Graphical User Interface), the various images are compressed and is implemented without affecting the original quality of the image. The SPIHT algorithm can be applied to both grey-scale and colored images. Comparison of SPIHT in both the arithmetic coder and pipelined architecture was enumerated in this paper. SPIHT displays exceptional characteristics over several properties like good images quality, fast coding and decoding, a fully progressive bit stream, application in lossless compressions, error protection and ability to code for exact bit rate. Key words-SPIHT, arithmetic coding, DWT, compression process, wavelet transform, encoder and decoder, offsprings, list of insignificant pixels (LIP), list of significant pixels (LSP), list of insignificant sets(LIS), VLSI arithmetic coder architecture.